Field of the Invention
The present invention relates to power saving of a data transfer apparatus in an information processing apparatus.
Description of the Related Art
Improvements in integration degree and processing capability of a semiconductor integrated circuit increases power consumption, making power saving measures essential.
Recent semiconductor integrated circuits include a master module generating a data transfer request, a slave module responding to the data transfer request, a bus system performing data transfer, and the like. The master module includes a central processing unit (CPU), a direct memory access controller (DMAC), and the like. The slave module includes a memory controller, a static random access memory (SRAM) module, and the like. The bus system is also referred to as an interconnect, fabric, on-chip network. In the master module, power is saved by a technique referred to as dynamic voltage and frequency scaling (DVFS) for dynamically controlling power supply voltage and frequency and a technique for shutting off the power supply and clock.
Conversely, the bus system to which various master modules and slave modules are connected is often in a state in which the power and clock are constantly supplied thereto for a data transfer request from each master module, making it difficult to further reduce the power consumption. When a clock frequency is switched and on/off of the clock or the power supply is controlled to reduce power consumption, transfer data may be lost or the system may freeze unless data transfer on the bus system is completed according to a specific procedure. Methods for avoiding loss of transfer data and freezing are roughly classified into a method using a software procedure and a method using a hardware mechanism.
A method using a software procedure generally controls the clock and the power supply of the bus system after confirming that no data transfer request is issued for all the master modules connected to the bus system. In addition, a method using a bus arbitration circuit is discussed as a method using a hardware mechanism (for example, Japanese Patent No. 4733877).
In recent large-scale semiconductor integration circuits, the number of master modules exceeds 100, and many master modules are driven by an external interrupt or event. Thus, using a software procedure method, it is difficult to ensure that none of the master modules have issued a data transfer request.
In addition, when the CPU controls the clock and the power supply of the bus system, an instruction fetch and a cache module of the CPU speculatively reads program data, so that a special procedure is required to ensure that on data transfer is performed on the bus system. Consequently, if the clock and the power supply of the bus system can be controlled, the opportunity to save power is very limited.
According to the method using the hardware mechanism described in Japanese Patent No. 4733877, when currently executed processing is ended, a bus arbitration circuit which arbitrates a bus use right in response to the assertion of a clock control request signal, stops assignment of the bus use right and asserts a clock control confirmation signal. However, a bus system using a peer-to-peer data transfer interface is a mainstream in recent years, and in the hardware mechanism described in Japanese Patent No. 4733877, the bus arbitration circuit exists in the bus system. The method using the bus arbitration circuit cannot shut off the power supply to the bus system itself.
In addition, as an issue specific to the power savings of the bus system, data transfer is generated in various timings from a plurality of master modules, and a power saving period for shutting off the clock and the power supply is divided into pieces, so that a power saving effect is limited.